A content addressable memory (CAM) is generally a memory device with two modes of access. In one mode, the CAM works as a normal random access memory--the contents of the memory are read and written at specified addresses. In a second mode, the CAM compares a specified string, often called the comparand, with the information stored in its memory cells and then generates signals which indicate if a match (i.e., between the comparand and any of the information in the memory) was found.
The present invention concerns the application of dynamic MOS memory technology to CAM cells. The inventors know of only four MOS dynamic CAM cells which have been described in the literature: J. L. Mundy, U.S. Pat. No. 3,701,980 (1972, assignee: General Electric Co.); R. M. Lea: "A Design for a Low-Cost, High-Speed MOS Associative Memory," The Radio and Electronic Engineer, Vol. 45, No. 4, April 1975; Y. Lavi, U.S. Pat. No. 4,377,855, granted 1983 (Assignee: National Semiconductor Corp.); J. P. Wade and C. G. Sodini, "Dynamic Cross-Coupled Bit-Line Content Addressable Memory Cell for High-Density Arrays," IEEE Journal of Solid State Circuits, Vol. SC-22, No. 1, February 1987. All of the dynamic CAM (DCAM) cells described in these references were designed using NMOS technology.
The primary goal of using dynamic memory technology, rather than static memory technology, is to achieve greater packing density. With regard to other (not CAM) memories, dynamic random access memory (DRAM) devices typically have four times the storage capacity of static random access memories (SRAM) using comparable technology. This capacity advantage, however, is bought at the expense of the need to refresh the dynamic storage element--a capacitor with a capacitance of about 50 femtofarads. Furthermore, dynamic memories have higher "soft error" rates because DRAM cells have a higher susceptibility to being affected by alpha-particle bombardment.
It is also known that CMOS dynamic memory devices have higher alpha-particle immunity than other dynamic memory devices, because the storage element in CMOS memories resides in a potential well which protects it from the electrical effects induced by alpha-particle bombardment.
The problem addressed by the present invention is that, in the prior art, the cell area advantage of dynamic CAM cells over static CAM cells is less than in the case of RAM technology. The dynamic CAM (DCAM) cells have not provided a sufficient cell area advantage to be commercially viable primarily because of the large area occupied by the comparison circuitry needed in every memory cell.